Machine Vision Coprocessors

In one of our early projects in machine vision [1], we demonstrated a face recognition system employing an image correlation chip capable of a 5x5 correlation on templates of size 68 x 68 pixels (target image) and 64x64 pixels (database image). This 60,000 transistor chip was implemented in 2.0um technology and was designed to operate at 5 MHz on a standard PC ISA card. A photo of the overall face recognition system is shown below:

Currently, we are working on the second generation of this image correlator hardware. A 180,000 transistor chip (which was shown on the previous page) has been realized in 0.6um technology, and is projected to operate at 100 MHz. The maximum image template size is now 128x128 (target) image, with a database image of 120x120 pixels and the correlation shift range is now 8x8. Like the chip described in [1], this chip is based on an architecture described more fully in [2] and [3] but incorporates several new features.

Each of the on-chip line buffers has been made variable in length and separately programmable. Decimation and interpolation of incoming images by a factor of two is now possible; in the case of decimation the chip can handle the edge extension which is required on odd-length images. It is possible to program the start of correlation both within the overall image and within each image row, making for variable size definition of the database image. The chip also includes minimum detection to rapidly output the minimum (best) correlation result and the address of the correlator processor which produced it. Since the correlation shift range is 8x8, there are 64 integrated correlator processors. Each processor incorporates a saturating accumulator which allows for the handling of much (x16) larger images length-wise than the 128 row figure, with lower accuracy.

The chip incorporates several programmable modes to take advantage of any of the above features as desired. Using these it is also possible to realise a number of multi-chip configurations, for example for implementing a 16x16 correlation within an MPEG environment, which requires four of these chips [4]. The chip is designed to interface to any general PC bus and design of an appropriate card to a PCI bus system is currently under development.

[1] J.M.Gilbert and W.Yang, "A Real-Time Face Recognition System Using Custom VLSI Hardware", Proceedings of the IEEE Workshop on Computer Architectures for Machine Perception, 58-66, 1993.

[2] P.Pirsch, N.Demassieux, and W.Gehrke, "VLSI Architectures for Video Compression - A Survey", Proceedings of the IEEE, vol 83, 1995.

[3] D.Vos, "Parametrizable VLSI Architectures for full-search block-matching algorithms", IEEE Transactions on Circuits & Systems, vol 36, 1989.

[4] A. Bugeja and W. Yang, "A Reconfigurable VLSI Coprocessing System for the Block Matching Algorithm", to appear in the IEEE Transactions on VLSI Systems. vol 36, 1989.